MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 442

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
14.2.3
Signals V
logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF,
X7R ceramic).
In shutdown mode an external supply at V
14.2.4
Signals V
PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In shutdown mode an external supply at V
14.2.5
This optional signal is used to shutdown VREG3V3V2. In that case V
be provided externally. shutdown mode is entered with V
VREG3V3V2 is either in full-performance mode or in reduced-power mode.
For the connectivity of V
14.3
This subsection provides a detailed description of all registers accessible in VREG3V3V2.
14.3.1
Figure 14-2
442
DDPLL
DD
Memory Map and Register Definition
Address
0x0000
Offset
V
V
V
Module Memory Map
provides an overview of all used registers.
/V
DD
DDPLL
REGEN
Switching from FPM or RPM to shutdown of VREG3V3V2 and vice versa
is not supported while the MCU is powered.
SS
/V
, V
are the primary outputs of VREG3V3V2 that provide the power supply for the core
SSPLL
SS
, V
— Optional Regulator Enable
— Regulator Output1 (Core Logic)
are the secondary outputs of VREG3V3V2 that provide the power supply for the
SSPLL
REGEN
see device overview chapter.
— Regulator Output2 (PLL)
VREG3V3V2 Control Register (VREGCTRL)
Table 14-2. VREG3V3V2 Memory Map
MC9S12E128 Data Sheet, Rev. 1.07
DD
DDPLL
/V
SS
/V
NOTE
can replace the voltage regulator.
Use
SSPLL
REGEN
can replace the voltage regulator.
being low. If V
DD
/V
SS
and V
REGEN
Freescale Semiconductor
DDPLL
is high, the
Access
R/W
/V
SSPLL
must