MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 362

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
In complementary channel operation, there are three additional features:
11.4.5
While in the complementary mode, each PWM pair can be used to drive top/bottom transistors, as shown
in
active, the bottom PWM channel is inactive, and vice versa.
Deadtime generators automatically insert software-selectable activation delays into each pair of PWM
outputs. The deadtime register (PMFDTMx) specifies the number of PWM clock cycles to use for
deadtime delay. Every time the deadtime generator inputs changes state, deadtime is inserted. Deadtime
forces both PWM outputs in the pair to the inactive state.
A method of correcting this, adding to or subtracting from the PWM value used, is discussed next.
362
Figure
GENERATOR
•
•
•
•
PWM
Deadtime insertion
Separate top and bottom pulse width correction for distortions are caused by deadtime inserted and
the motor drive characteristics
Separate top and bottom output polarity control
Swap functionality
11-49. Ideally, the PWM pairs are an inversion of each other. When the top PWM channel is
Deadtime Generators
To avoid a short-circuit on the DC bus and endangering the transistor, there
must be no overlap of conducting intervals between top and bottom
transistor. But the transistor’s characteristics make its switching-off time
longer than switching-on time. To avoid the conducting overlap of top and
bottom transistors, deadtime needs to be inserted in the switching period.
CURRENT
STATUS
PWM0 &
PWM1
PWM2 &
PWM3
PWM4 &
PWM5
OUT0
OUT2
OUT4
Figure 11-49. Deadtime Generators
MC9S12E128 Data Sheet, Rev. 1.07
OUTCTL0
OUTCTL2
OUTCTL4
MUX
MUX
MUX
NOTE
GENERATOR
GENERATOR
GENERATOR
DEADTIME
DEADTIME
DEADTIME
OUT1
OUT3
OUT5
TOP/BOTTOM
TOP/BOTTOM
TOP/BOTTOM
GENERATOR
GENERATOR
GENERATOR
TOP (PWM0)
BOTTOM (PWM1)
TOP (PWM2)
BOTTOM (PWM3)
TOP (PWM4)
BOTTOM (PWM5)
Freescale Semiconductor
TO FAULT
PROTECTION
TO FAULT
PROTECTION
TO FAULT
PROTECTION