MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 455

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

15.3.2.2
Read: All modes
Write: All modes
When entering background debug mode, the BDM CCR holding register is used to save the contents of the
condition code register of the user’s program. It is also used for temporary storage in the standard BDM
firmware mode. The BDM CCR holding register can be written to modify the CCR value.
15.3.2.3
Read: All modes
Write: Never
Freescale Semiconductor
REG[14:11]
Reset
Reset
Field
6:3
W
W
R
R
CCR7
Internal Register Map Position — These four bits show the state of the upper five bits of the base address for
the system’s relocatable register block. BDMINR is a shadow of the INITRG register which maps the register
block to any 2K byte space within the first 32K bytes of the 64K byte address space.
BDM CCR Holding Register (BDMCCR)
BDM Internal Register Position Register (BDMINR)
0
0
0
7
7
When BDM is made active, the CPU stores the value of the CCR register in
the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register.
= Unimplemented or Reserved
REG14
CCR6
0
0
Figure 15-5. BDM Internal Register Position (BDMINR)
6
6
Figure 15-4. BDM CCR Holding Register (BDMCCR)
Table 15-4. BDMINR Field Descriptions
REG13
CCR5
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
5
REG12
CCR4
NOTE
0
0
4
4
Description
REG11
CCR3
0
0
3
3
Chapter 15 Background Debug Module (BDMV4)
CCR2
0
0
0
2
2
CCR1
0
0
0
1
1
CCR0
0
0
0
0
0
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