HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 226

• Manufacturer Part Number: HD64F2378RVFQ33
• Description: IC H8S MCU FLASH 512K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2378RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Bit
10
9
8
7
Rev.7.00 Mar. 18, 2009 page 158 of 1136
REJ09B0109-0700
Bit Name
RMTS2
RMTS1
RMTS0
BE
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
DRAM/Continuous Synchronous DRAM Space
Select
These bits designate DRAM/continuous
synchronous DRAM space for areas 2 to 5.
When continuous DRAM space is set, it is possible
to connect large-capacity DRAM exceeding 2
Mbytes per area. In this case, the RAS signal is
output from the CS2 pin.
When continuous synchronous DRAM space is set,
it is possible to connect large-capacity synchronous
DRAM exceeding 2 Mbytes per area. In this case,
the RAS, CAS, and WE signals are output from
CS2, CS3, and CS4 pins, respectively. When
synchronous DRAM mode is set, the mode
registers of the synchronous DRAM can be set.
000: Normal space
001: Normal space in areas 3 to 5
010: Normal space in areas 4 and 5
011: DRAM space in areas 2 to 5
100: Continuous synchronous DRAM space
101: Synchronous DRAM mode setting (setting
110: Setting prohibited
111: Continuous DRAM space in areas 2 to 5
Burst Access Enable
Selects enabling or disabling of burst access to
areas designated as DRAM/continuous
synchronous DRAM space. DRAM/continuous
synchronous DRAM space burst access is
performed in fast page mode. When using EDO
page mode DRAM, the OE signal must be
connected.
0: Full access
1: Access in fast page mode
DRAM space in area 2
DRAM space in areas 2 and 3
(setting prohibited in the H8S/2378 Group)
prohibited in the H8S/2378 Group)