HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 455

• Manufacturer Part Number: HD64F2378RVFQ33
• Description: IC H8S MCU FLASH 512K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2378RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC)
EXDMA Transfer Count Register (EDTCR): When a DMA transfer is performed, the value in
EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and
the EDTCR value does not change.
EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to
specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function
as a transfer counter, the value of which is decremented by 1 when a DMA transfer is performed.
However, when the EDTCR[15:0] value is 0, transfers are not counted and the EDTCR[15:0]
value does not change.
In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read
by the CPU during DMA transfer, a longword access must be used. During a transfer operation,
EDTCR may be updated without regard to accesses from the CPU, and the correct values may not
be read if the upper and lower words are read separately. In a longword access, the EXDMAC
buffers the EDTCR value to ensure that the correct value is output.
In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word
access.
Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is
contention between an address update associated with DMA transfer and a write by the CPU, the
CPU write has priority.
In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value)
by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated.
Transfer does not end if the CPU writes 0 to EDTCR.
Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.
Rev.7.00 Mar. 18, 2009 page 387 of 1136
REJ09B0109-0700