HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 495

• Manufacturer Part Number: HD64F2378RVFQ33
• Description: IC H8S MCU FLASH 512K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2378RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.2
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set
of register information that is stored in an on-chip RAM to the corresponding DTC registers and
transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to H (DTCERA to DTCERH)
• DTC vector register (DTVECR)
9.2.1
MRA selects the DTC operating mode.
Bit
7
6
Bit Name
SM1
SM0
Register Descriptions
DTC Mode Register A (MRA)
Initial Value
Undefined
Undefined
R/W
—
—
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0×: SAR is fixed
10: SAR is incremented after a transfer
11: SAR is decremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
Rev.7.00 Mar. 18, 2009 page 427 of 1136
Section 9 Data Transfer Controller (DTC)
REJ09B0109-0700