HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 35

IC H8S MCU FLASH 512K 144-LQFP

HD64F2378RVFQ33

Manufacturer Part Number
HD64F2378RVFQ33
Description
IC H8S MCU FLASH 512K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of HD64F2378RVFQ33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
11.5 Interrupt Sources ................................................................................................................ 609
11.6 DTC Activation.................................................................................................................. 611
11.7 DMAC Activation.............................................................................................................. 611
11.8 A/D Converter Activation .................................................................................................. 611
11.9 Operation Timing............................................................................................................... 612
11.10 Usage Notes ....................................................................................................................... 619
Section 12 Programmable Pulse Generator (PPG) ............................................631
12.1 Features .............................................................................................................................. 631
12.2 Input/Output Pins ............................................................................................................... 633
12.3 Register Descriptions ......................................................................................................... 633
12.4 Operation............................................................................................................................ 641
11.4.5 PWM Modes ......................................................................................................... 598
11.4.6 Phase Counting Mode ........................................................................................... 603
11.9.1 Input/Output Timing ............................................................................................. 612
11.9.2 Interrupt Signal Timing......................................................................................... 615
11.10.1 Module Stop Mode Setting ................................................................................... 619
11.10.2 Input Clock Restrictions ....................................................................................... 619
11.10.3 Caution on Cycle Setting ...................................................................................... 620
11.10.4 Contention between TCNT Write and Clear Operations ...................................... 620
11.10.5 Contention between TCNT Write and Increment Operations............................... 621
11.10.6 Contention between TGR Write and Compare Match .......................................... 622
11.10.7 Contention between Buffer Register Write and Compare Match ......................... 623
11.10.8 Contention between TGR Read and Input Capture............................................... 624
11.10.9 Contention between TGR Write and Input Capture.............................................. 625
11.10.10 Contention between Buffer Register Write and Input Capture .......................... 626
11.10.11 Contention between Overflow/Underflow and Counter Clearing...................... 627
11.10.12 Contention between TCNT Write and Overflow/Underflow............................. 628
11.10.13 Multiplexing of I/O Pins .................................................................................... 629
11.10.14 Interrupts and Module Stop Mode ..................................................................... 629
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL).......................................... 634
12.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 635
12.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 635
12.3.4 PPG Output Control Register (PCR)..................................................................... 638
12.3.5 PPG Output Mode Register (PMR)....................................................................... 639
12.4.1 Output Timing....................................................................................................... 642
12.4.2 Sample Setup Procedure for Normal Pulse Output ............................................... 643
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) ........... 644
12.4.4 Non-Overlapping Pulse Output............................................................................. 645
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ............................... 647
Rev.7.00 Mar. 18, 2009 page xxxiii of lxvi
REJ09B0109-0700

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