HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 880
![IC H8S MCU FLASH 512K 144-LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
HD64F2378RVFQ33
Manufacturer Part Number
HD64F2378RVFQ33
Description
IC H8S MCU FLASH 512K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2378RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 17 A/D Converter
17.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
17.4.1
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
17.4.2
In scan mode, A/D conversion is to be performed sequentially on the specified channels:
maximum four channels or maximum eight channels. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by a software, TPU or external trigger input, A/D
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
Rev.7.00 Mar. 18, 2009 page 812 of 1136
REJ09B0109-0700
or external trigger input.
register to the channel.
this time, an ADI interrupt request is generated.
conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion
stops and the A/D converter enters wait state.
conversion starts on the first channel in the group.
The consecutive A/D conversion on maximum four channels (SCANE and SCANS = 10) or on
maximum eight channels (SCANE and SCANS = 11) can be selected. When the consecutive
A/D conversion is performed on the four channels, the A/D conversion starts on AN0 when
CH3 and CH2 =00, AN4 when CH3 and CH2 = 01, AN8 when CH3 and CH2 = 10, or AN12
when CH3 and CH2 = 11. When the consecutive A/D conversion is performed on the eight
channels, the A/D conversion starts on AN0 when SH3 =0 and on AN8 when SH3 =1.
the corresponding A/D data register to each channel.
Operation
Single Mode
Scan Mode
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