HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 319

• Manufacturer Part Number: HD64F2378RVFQ33
• Description: IC H8S MCU FLASH 512K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2378RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1
in BCR, an idle cycle is inserted at the start of the read cycle.
Figure 6.67 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
Address bus
CS (area A)
CS (area B)
HWR, LWR
Data bus
RD
Figure 6.67 Example of Idle Cycle Operation (Read after Write)
φ
(a) No idle cycle insertion
T
(ICIS2 = 0)
1
Bus cycle A
Long output floating time
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
Rev.7.00 Mar. 18, 2009 page 251 of 1136
φ
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS2 = 1, initial value)
Section 6 Bus Controller (BSC)
T
2
T
3
Idle cycle
T
i
Bus cycle B
REJ09B0109-0700
T
1
T
2