HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 843
![IC H8S MCU FLASH 512K 144-LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
HD64F2378RVFQ33
Manufacturer Part Number
HD64F2378RVFQ33
Description
IC H8S MCU FLASH 512K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2378RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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16.3.1
ICCRA is an 8-bit readable/writable register that enables or disables the I
transmission or reception, and selects master or slave mode, transmission or reception, and
transfer clock frequency in master mode.
Bit
7
6
5
4
3
2
1
0
Bit Name
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
I
2
C Bus Control Register A (ICCRA)
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I
0: This module is halted.
1: This bit is enabled for transfer operations. (SCL
Reception Disable
This bit enables or disables the next operation
when TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
When arbitration is lost in master mode, MST and
TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of the
TRS bit should be made between transfer frames.
In addition, TRS is set to 1 automatically in slave
receive mode if the seventh bit of the start condition
matches the slave address set in SAR and the
eighth bit is set to 1.
Operating modes are described below according to
MST and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer clock select 3 to 0
In the master mode, these bits should be set
according to the necessary transfer rate (see table
16.2). In the slave mode, they are used to secure
the data setup time in transmit mode. The data
setup time is 10 tcyc if CKS3 is cleared to 0 and 20
tcyc if CKS3 is set to 1.
2
C Bus Interface Enable
and SDA pins are bus drive state.)
Section 16 I
Rev.7.00 Mar. 18, 2009 page 775 of 1136
2
C Bus Interface 2 (IIC2) (Option)
2
C bus interface, controls
REJ09B0109-0700
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