SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet - Page 118

• Manufacturer Part Number: SI1000-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1000-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Cpu Family: Si100x
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 25MHz
• Total Internal Ram Size: 4.25KB
• # I/os (max): 22
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 18-chx10-bit
• Instruction Set Architecture: CISC
• Mounting: Surface Mount
• Pin Count: 42
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1881-5

Si1000/1/2/3/4/5
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si1000/1/2/3/4/5 device family is shown in Figure 9.1
118
0x7FFF
0xFBFF
0x03FF
PR OG RAM /DA TA M EM O R Y
0xFFFF
0xFC00
0x0000
0x03FF
0x0000
0x0000
0x0000
Program m able in 1024
Program m able in 1024
(FLA SH)
Scrachpad M em ory
Scrachpad M em ory
64KB FLASH
Byte Sectors)
32KB FLASH
Byte Sectors)
(D ATA only)
R ESER VED
(D ATA only)
(In-System
(In-System
Si1000/2
Si1001/3
Figure 9.1. Si1000/1/2/3/4/5 Memory Map
Rev. 1.0
(Indirect Addressing O nly)
(D irect and Indirect
G eneral Purpose
U pper 128 R AM
Bit Addressable
Addressing)
R egisters
EXTERNAL DATA ADDR ESS SPACE
0xFFFF
0x0FFF
0x1000
0x0000
INTERN AL DATA ADDR ESS SPACE
DATA M EM O RY
XR AM - 4096 Bytes
(accessable using M O VX
(R AM )
instruction)
Reserved
(D irect Addressing O nly)
Low er 128 RAM
(D irect and Indirect
Addressing)
Special Function
R egisters
0
F