SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet - Page 176

• Manufacturer Part Number: SI1000-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1000-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Cpu Family: Si100x
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 25MHz
• Total Internal Ram Size: 4.25KB
• # I/os (max): 22
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 18-chx10-bit
• Instruction Set Architecture: CISC
• Mounting: Surface Mount
• Pin Count: 42
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1881-5

Si1000/1/2/3/4/5
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
V
Figure 18.3 plots the power-on and V
power-on reset delay (T
3.6 V).
Note: The maximum V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
Note: Si1000/1/2/3 have the VBAT signal internally connected to VDD_MCU.
176
POR
BAT
. An additional delay occurs before the device is released from reset; the delay decreases as the
ramp time increases (V
before V
See specification
table for min/max
voltages.
BAT
reaches the V
Logic HIGH
Logic LOW
~0.8
~0.5
DD
0.6
PORDelay
ramp time is 3 ms; slower ramp times may cause the device to be released from reset
Figure 18.2. Power-Fail Reset Timing Diagram
POR
RST
BAT
) is typically 3 ms (V
level.
ramp time is defined as how fast V
V
POR
DD
monitor reset timing. For valid ramp times (less than 3 ms), the
Power-On
Reset
Rev. 1.0
T
PORDelay
BAT
= 0.9 V), 7 ms (V
Power-On
Reset
BAT
BAT
ramps from 0 V to V
= 1.8 V), or 15 ms (V
T
PORDelay
BAT
VBAT
settles above
t
BAT
POR
).
=