SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet - Page 158

• Manufacturer Part Number: SI1000-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1000-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Cpu Family: Si100x
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 25MHz
• Total Internal Ram Size: 4.25KB
• # I/os (max): 22
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 18-chx10-bit
• Instruction Set Architecture: CISC
• Mounting: Surface Mount
• Pin Count: 42
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1881-5

Si1000/1/2/3/4/5
15. Cyclic Redundancy Check Unit (CRC0)
Si1000/1/2/3/4/5 devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a
16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0
posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indi-
rectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15.1. CRC0 also has a bit
reverse register for quick data manipulation.
15.1. CRC Algorithm
The Si1000/1/2/3/4/5 CRC unit generates a CRC result equivalent to the following algorithm:
1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration of the
2a. If the MSB of the CRC result is set, shift the CRC result and XOR the result with the selected
2b. If the MSB of the CRC result is not set, shift the CRC result.
Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following exam-
ple.
The 16-bit Si1000/1/2/3/4/5 CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
158
CRC unit, the current CRC result will be the set initial value 
(0x00000000 or 0xFFFFFFFF).
polynomial.
unsigned char i;
#define POLY 0x1021
CRC0FLIP
CRC0FLIP
CRC0PNT1
CRC0PNT0
CRC0SEL
CRC0INIT
CRC0VAL
Write
Read
Figure 15.1. CRC0 Block Diagram
CRC0IN
8
// loop counter
CRC Engine
Rev. 1.0
8
8
RESULT
4 to 1 MUX
32
8
8
8
Automatic CRC
8
Controller
CRC0AUTO
CRC0DAT
CRC0CNT
Memory
Flash