SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet - Page 177

• Manufacturer Part Number: SI1000-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1000-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Cpu Family: Si100x
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 25MHz
• Total Internal Ram Size: 4.25KB
• # I/os (max): 22
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 18-chx10-bit
• Instruction Set Architecture: CISC
• Mounting: Surface Mount
• Pin Count: 42
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1881-5

18.2. Power-Fail (VDD_MCU Supply Monitor) Reset
Si1000/1/2/3/4/5 devices have a VDD_MCU Supply Monitor that is enabled and selected as a reset source
after each power-on or power-fail reset. When enabled and selected as a reset source, any power down
transition or power irregularity that causes VDD_MCU to drop below V
driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD_MCU returns to a
level above V
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and theVDD_MCU supply
monitor is enabled and selected as a reset source. The enable state of the VDD_MCU supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD_MCU supply monitor is de-selected as a reset source and disabled by software, then a software
reset is performed, the VDD_MCU supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in sleep mode prior to a power-fail reset occurring. When the device is in sleep
mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below V
above V
source select state of the VDD_MCU supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD_MCU supply falls below the V
interrupt. See Section “12. Interrupt Handler” on page 129 for more details.
Important Note: To protect the integrity of Flash contents, the VDD_MCU supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD_MCU supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
V
V
V
POR
WARN
POR
RST
VDDOK
SLEEP
while the user is replacing the battery. Upon waking from sleep mode, the enable and reset
RST
RST
, the CIP-51 will be released from the reset state.
Pow er-Fail R eset
Active M ode
Figure 18.3. Power-Fail Reset Timing Diagram
VDD_MCU/DC+
POR
VBAT
. A large capacitor can be used to hold the power supply voltage
WARN
threshold. The VDDOK bit can be configured to generate an
Rev. 1.0
R AM Retained - No Reset
Sleep M ode
RST
Si1000/1/2/3/4/5
will cause the RST pin to be
N ote: W akeup signal
required after new
battery insertion
t
177