EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 323

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 1–6. External Clock Outputs for Enhanced PLLs 11 & 12
Note to
(1)
Altera Corporation
July 2005
Counter
3.3-V GTL+
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-3 Class I
SSTL-3 Class II
AGP (1× and 2×)
CTT
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
g 0
For PLL11, this pin is CLK13n; for PLL 12 this pin is CLK6n.
Figure
From Internal
I/O Standard
Logic or IOE
1–6:
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure
Therefore, to minimize jitter, do not place switching I/O pins next to this
output pin.
INCLK
1–6). These outputs do not have their own VCC and GND signals.
v
v
v
v
v
v
v
v
v
v
v
v
v
General-Purpose PLLs in Stratix & Stratix GX Devices
Input
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix Device Handbook, Volume 2
PLLENABLE
or CLK6n, I/O, PLL12_OUT (1)
CLK13n, I/O, PLL11_OUT
EXTCLK
Output
v
v
v
v
v
v
v
v
v
v
v
v
v
1–13