EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 490

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Differential I/O Interface & Fast PLLs
5–18
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
ENA
FPLL7CLK
FPLL8CLK
FPLL9CLK
FPLL10CLK
Table 5–3. Fast PLL Clock Inputs (Including Feedback Clocks) & Enables
Input Pin
PLLs 5, 6, 11, and 12 are not fast PLLs.
Clock pins CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip
termination.
Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8, PLL9, and PLL10) when used for
general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode.
(2)
(2)
(2)
(2)
Table
5–3:
PLL 1
v
v
v
Clock Input & Fast PLL Output Relationship
Table 5–3
signal (ENA).
connect to across all Stratix family devices.
All Stratix Devices
PLL 2
v
v
v
summarizes the PLL interface to the input clocks and the enable
PLL 3
Table 5–4
v
v
v
PLL 4
summarizes the clock networks each fast PLL can
v
v
v
PLL 7
v
v
v
(3)
EP1S30 to EP1S80 Devices Only
Note (1)
PLL 8
v
v
v
(3)
v
PLL 9
Altera Corporation
(3)
v
v
v
July 2005
PLL 10
(3)
v
v