EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 383

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 2–8. Shift-Register Memory Configuration
Altera Corporation
July 2005
w
w
w
w
w × m × n Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift-register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle.
TriMatrix memory block in the shift-register mode.
Implementing ROM Mode
The M512 and the M4K blocks support ROM mode. Use a memory
initialization file (.mif) to initialize the ROM contents of M512 and M4K
blocks. The M-RAM block does not support ROM mode.
All Stratix memory configurations must have synchronous inputs;
therefore, the address lines of the ROM are registered. The outputs can be
registered or combinatorial. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
Figure 2–8
w
w
w
w
shows the
n Number
of Taps
2–15