EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 405

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 3–6. t
Altera Corporation
June 2006
dataout
datain
clock
wren
addr
ZX
& t
A1
f
XZ
Timing Diagram
than the clock-to-high-impedance time (t
I/O pins can interface with ZBT SRAM devices at up to 200 MHz and can
meet ZBT t
clocks to the OE or output and input registers using an enhanced PLL.
Figure 3–6
are read addresses and A2 and A4 are write addresses. For pipelined
ZBT SRAM operation, data is delayed by another clock cycle. Stratix and
Stratix GX devices support up to 200-MHz ZBT SRAM operation using
the 2.5-V or 3.3-V LVTTL I/O standard.
Interface Pins
ZBT SRAM uses one system clock input for all clocking purposes. Only
the rising edge of this clock is used, since ZBT SRAM uses a single data
rate scheme. The data bus, DQ, is bidirectional. There are three control
signals to the ZBT SRAM: RW_N, BW_N, and ADV_LD_N. You can use any
of the Stratix and Stratix GX device user I/O pins to interface to the
ZBT SRAM device.
For more information on ZBT SRAM Interfaces in Stratix devices, see
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX
Devices.
ZBT Bus Sharing
A2
Device t
shows a flow-through ZBT SRAM operation where A1 and A3
CO
Q(A1)
and t
ZX
External Memory Interfaces in Stratix & Stratix GX Devices
SU
timing requirements by controlling phase delay in
A3
t
XZ
D(A3)
Stratix Device Handbook, Volume 2
XZ
A4
). Stratix and Stratix GX device
t
ZX
Q(A3)
3–9