EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 439

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
June 2006
Figure 4–10. SSTL-2 Class II Termination
SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3
The SSTL-18 I/O standard is a 1.8-V memory bus standard. This standard
is similar to SSTL-2 and defines input and output specifications for
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V V
series and termination resistors are connected. See
for details on SSTL-18 Class I and II termination. Stratix and Stratix GX
devices support both input and output levels.
Figure 4–11. SSTL-18 Class I Termination
Figure 4–12. SSTL-18 Class II Termination
Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A
The differential SSTL-2 I/O standard is a 2.5-V standard used for
applications such as high-speed DDR SDRAM clock interfaces. This
standard supports differential signals in systems using the SSTL-2
Output Buffer
Output Buffer
Output Buffer
Selectable I/O Standards in Stratix & Stratix GX Devices
25 Ω
25 Ω
25 Ω
V
V
TT
TT
= 1.25 V
= 0.9 V
V
V
50 Ω
REF
50 Ω
V
REF
Z = 50 Ω
REF
Z = 50 Ω
Z = 50 Ω
= 0.9 V
= 1.25 V
= 0.9 V
V
TT
REF
V
V
Stratix Device Handbook, Volume 2
TT
TT
= 0.9 V
and a 0.9-V V
= 1.25 V
= 0.9 V
50 Ω
50 Ω
50 Ω
Figures 4–11
Input Buffer
Input Buffer
Input Buffer
TT
to which the
and
4–12
4–11