EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 333

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 1–12. Effect of High Bandwidth on Clock Switchover
Altera Corporation
July 2005
Frequency (MHz)
160
155
150
145
140
135
130
125
0
2
Implementation
Traditionally, external components such as the VCO or loop filter control
a PLL’s bandwidth. Most loop filters are made up of passive components,
such as resistors and capacitors, which take up unnecessary board space
and increase cost. With Stratix and Stratix GX device enhanced PLLs, all
the components are contained within the device to increase performance
and decrease cost.
Stratix and Stratix GX device enhanced PLLs implement programmable
bandwidth by giving you control of the charge pump current and loop
filter resistor (R) and high-frequency capacitor (C
Table
ranges from approximately 150 kHz to 2 MHz.
Initial Lock
4
1–8). The Stratix and Stratix GX device enhanced PLL bandwidth
6
General-Purpose PLLs in Stratix & Stratix GX Devices
8
Time (μs)
Input Clock Stops
10
Switchover
12
Stratix Device Handbook, Volume 2
14
h
) values (see
Re-lock
16
18
1–23
20