EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 662

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Interfaces
8–18
Stratix Device Handbook, Volume 2
f
V HSTL I/O pins for data and control and 2 clock pins for the transmitter
and receiver clocks. Each XGMII core also needs two PLLs (one for each
direction).
Reduced System Noise
The output buffer of each Stratix and Stratix GX device I/O pin has a
programmable drive strength control for certain I/O standards. The 1.5-
V HSTL Class I standard supports the minimum setting, which is the
lowest drive strength that guarantees I
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot.
For more information on I
the DC & Switching Characteristics chapter of the Stratix Device Handbook,
Volume 1 or Operating Conditions in the DC & Switching Characteristics
chapter of the Stratix GX Device Handbook, Volume 1.
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
EP1SGX10 C, D
EP1SGX25 C
EP1SGX25 D, F
EP1SGX40 D, G
Table 8–6. Stratix XGMII Core Support
Table 8–7. Stratix GX XGMII Core Support
Stratix Device
Stratix Device
Number of 1.5-V
Number of 1.5-V
HSTL Class I I/O
HSTL Class I I/O
1,014
1,195
Pins
Pins
OH
410
570
690
718
814
226
253
370
430
and I
OL
values, see Operating Conditions in
OH
Number of Fast
Number of Fast
& Enhanced
& Enhanced
and I
PLLs
PLLs
10
12
12
12
6
6
6
4
4
4
8
OL
of the standard. Using
Altera Corporation
Number of XGMII
Number of XGMII
Interfaces
Interfaces
3
3
3
5
6
6
6
2
2
2
4
July 2005