EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 595

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
user needs a way to accept this sample data and send it at a 4r rate to the
input of the DSP block. One way to do this is using a first-in-first-out
(FIFO) memory with input clocked at rate r and output clocked at rate 4r.
The FIFO may be implemented in the TriMatrix memory.
TDM Filter Implementation Results
Table 7–8
FIR filter as shown in
TDM Filter Design Example
Download the TDM FIR Filter (tdm_fir.zip) design example from the
Design Examples section of the Altera web site at www.altera.com.
Polyphase FIR Interpolation Filters
An interpolation filter can be used to increase sample rate. An
interpolation filter is efficiently implemented with a polyphase FIR filter.
DSP systems frequently use polyphase filters because they simplify
overall system design and also reduce the number of computations per
cycle required of the hardware. This section first describes interpolation
filters and then how to implement them as polyphase filters in Stratix and
Stratix GX devices. See the
page 7–24
Interpolation Filter Basics
An interpolation filter increases the output sample rate by a factor of I
through the insertion if I-1 zeros between input samples, a process
known as zero padding. After the zero padding, the output samples in
time domain are separated by Ts/I = 1/(I f
sample period and sample frequency of the original signal, respectively.
Figure 7–10
Note to
(1)
Part
Utilization
Performance
Table 7–8. TDM Filter Implementation Results
This refers to the performance of the DSP blocks. The input and output rate is 120
million samples per second (MSPS), clocked in and out at 120 MHz.
Table
shows the results of the implementation of an 18-bit 8-tap TDM
section for a discussion of decimation filters.
shows the concept of signal interpolation.
7–8:
EP1S10F780
Lcell: 196/10570 (1%)
DSP Block 9-bit elements: 8/48 (17%)
Memory bits: 360/920448 (<1%)
240 MHz
Figure 7–9 on page
“Polyphase FIR Decimation Filters” on
(1)
Stratix Device Handbook, Volume 2
7–16.
s
), where T
s
and f
s
are the
7–17