EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 687

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Altera Corporation
July 2005
cascade primitives in APEX II and APEX 20K designs to a wire primitive
when compiled for Stratix and Stratix GX devices. These architectural
changes are transparent to the user and do not require design changes.
Figure 10–1. Carry Chain Implementation in APEX II & APEX 20K Devices vs.
Stratix & Stratix GX Devices
MultiTrack Interconnect
Stratix and Stratix GX devices use the MultiTrack interconnect structure
to provide a high-speed connection between logic resources using
performance-optimized routing channels of different lengths. This
feature maximizes overall design performance by placing critical paths
on routing lines with greater speed, resulting in minimal propagation
delay.
APEX II & APEX 20K Devices
LABs (with 10 LEs Each)
Transitioning APEX Designs to Stratix & Stratix GX Devices
Carry Chains
Stratix Device Handbook, Volume 2
Stratix Devices
Carry-Select
Chains
10–3

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