EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 342

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Fast PLLs
Figure 1–17. Stratix & Stratix GX Fast PLL Block Diagram
Notes to
(1)
(2)
(3)
1–32
Stratix Device Handbook, Volume 2
Global or
regional clock (1)
Clock
Input
The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix and Stratix GX
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
Figure
1–17:
Frequency
Detector
general purpose abilities of the Fast PLL. For information on the high-
speed differential I/O interface capabilities, see the High-Speed Differential
I/O Interfaces in Stratix Devices chapter.
Phase
PFD
Charge
Pump
Loop
Filter
VCO Phase Selection
Selectable at each PLL
Output Port
÷m
VCO
8
Post-Scale
Counters
÷g0
÷l0
÷l1
Altera Corporation
diffioclk1 (2)
Global or
regional clock
txload_en (3)
rxload_en (3)
Global or
regional clock
diffioclk2 (2)
Global or
regional clock
July 2005