EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 820

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Combining MAX Devices & Flash Memory
Figure 12–24. Specifying Block Addresses for Application Configuration
Combining MAX
Devices & Flash
Memory
12–42
Stratix Device Handbook, Volume 2
For adding a new application configuration, follow the steps listed above
with one modification. In Step 5, select SOF Data and click on Properties.
In the SOF Data Properties dialog box, select a new page (for example,
page 3) and specify the addressing mode information. Continue with
steps 7 through 10. When a new page is added, the memory map output
file lists the start/end addresses for this page. A sample is shown below:
This section describes remote system configuration with the Stratix or
Stratix GX device and the Nios embedded processor, using a combination
of MAX
You can use MAX 3000 or MAX 7000 devices and an industry-standard
flash memory device instead of enhanced configuration devices. In this
scheme, flash memory stores configuration data, and the MAX device
controls reading and writing to the flash memory, keeping track of
address locations.
The MAX device determines which address location and at what length
to store configuration data in flash memory. The Nios embedded
processor, running in the Stratix or Stratix GX device, receives the
OPTION BITS
PAGE 3
®
devices and flash memory.
Block
0x00010000
0x0012FFFA
Start Address
0x0001003F
0x00174EB4
Altera Corporation
End Address
September 2004