EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 329

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 1–8. Open- & Closed-Loop Response Bode Plots
Altera Corporation
July 2005
Open-Loop Reponse Bode Plot
Closed-Loop Reponse Bode Plot
Gain
Gain
0 dB
A high-bandwidth PLL provides a fast lock time and tracks jitter on the
reference clock source, passing it through to the PLL output. A low-
bandwidth PLL filters out reference clock jitter, but increases lock time.
Stratix device enhanced PLLs allow you to control the bandwidth over a
General-Purpose PLLs in Stratix & Stratix GX Devices
Frequency
Frequency
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
Stratix Device Handbook, Volume 2
1–19