EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 390

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Clock Modes
Figure 2–12. Read/Write Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
(3)
2–22
Stratix Device Handbook, Volume 2
wraddress[ ]
address[ ]
byteena[ ]
wrclocken
rdclocken
wrclock
rdclock
data[ ]
For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
wren
rden
Figure
8 LAB Row
Clocks
8
2–12:
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Generator
Read
Pulse
Notes
Data In
Read Address
Write Address
Byte Enable
Read Enable
Write Enable
Memory Block
(1), (2),
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
(3)
D
ENA
Q
Altera Corporation
To MultiTrack
Interconnect
July 2005