EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 466

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Power Source of Various I/O Standards
Power Source of
Various I/O
Standards
Quartus II
Software
Support
4–38
Stratix Device Handbook, Volume 2
For Stratix and Stratix GX devices, the I/O standards are powered by
different power sources. To determine which source powers the input
buffers, see
You specify which programmable I/O standards to use for Stratix and
Stratix GX devices with the Quartus II software. This section describes
Quartus II implementation, placement, and assignment guidelines,
including
Compiler Settings
You make Compiler settings in the Compiler Settings dialog box
(Processing menu). Click the Chips & Devices tab to specify the device
family, specific device, package, pin count, and speed grade to use for
your design.
2.5V/3.3V LVTTL
PCI/PCI-X 1.0
AGP
1.5V/1.8V
GTL
GTL+
SSTL
HSTL
CTT
LVDS
LVPECL
PCML
HyperTransport
Table 4–13. The Relationships Between Various I/O Standards and the
Power Sources
Compiler Settings
Device & Pin Options
Assign Pins
Programmable Drive Strength Settings
I/O Banks in the Floorplan View
Auto Placement & Verification
Table
I/O Standard
4–13. All output buffers are powered by V
Power Source
V
V
V
V
V
V
V
V
V
V
V
V
V
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCINT
CCIO
CCIO
CCIO
CCIO
Altera Corporation
CCIO
June 2006
.

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