EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 753

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 11–19. PPA Timing Waveforms Using Strobed nRS & nWS Signals
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
The user can toggle nCS or CS during configuration if the design meets the specification for t
Device I/O pins are in user mode.
The DATA[7..0] pins are available as user I/Os after configuration and the state of theses pins depends on the
dual-purpose pin settings. Do not leave DATA[7..0] floating. If these pins are not used in user-mode, you should
drive them high or low, whichever is more convenient.
DATA7 is a bidirectional pin. It represents an input for data input, but represents an output to show the status of
RDYnBSY.
DATA7/RDYnBSY (4)
Figure
CONF_DONE
11–19:
INIT_DONE
DATA[7..0]
nCONFIG
nSTATUS
User I/O
nCS (1)
CS (1)
nWS
nRS
t
CF2SCD
Figure 11–19
using strobed nRS and nWS signals.
t
CFG
t
WSP
t
WS2RS
t
CF2WS
t
CF2ST0
t
t
STATUS
t
CF2ST1
t
RDY2WS
RSD7
Byte 0
shows the Stratix and Stratix GX timing waveforms when
t
DSU
t
CSH
t
DH
Byte 1
t
RS2WS
t
t
CSSU
WS2RS
Configuring Stratix & Stratix GX Devices
t
WS2B
t
BUSY
Byte n
Stratix Device Handbook, Volume 2
CSSU
t
CD2UM
, t
(3)
(2)
(2)
(2)
(2)
(2)
(2)
WSP
, and t
11–35
CSH
.