LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 100

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
7.2.8
7.2.8.1
7.2.9
Auto-Negotiation LP Acknowledge
Link Down (Link Status Negated)
Auto-Negotiation Page Received
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are
clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. RXCLK is the
output clock for the internal MII bus. It is recovered from the received data to clock the RXD bus. If
there is no received signal, it is derived from the system reference clock.
PHY Management Control
The PHY Management Control block is responsible for the management functions of the PHY,
including register access and interrupt generation. A Serial Management Interface (SMI) is used to
support registers 0 through 6 as required by the IEEE 802.3 (Clause 22), as well as the vendor specific
registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO)
signal and the MII Management Clock (MDC) signal. These signals interface to the MDIO and MDC
pins of LAN9303/LAN9303i (or the PMI block in I
registers. Refer to
registers and register descriptions. Non-supported registers will be read as FFFFh.
PHY Interrupts
The PHY contains the ability to generate various interrupt events as described in
the
the interrupt, and clears the interrupt signal. The
(PHY_INTERRUPT_MASK_x)
block aggregates the enabled interrupts status into an internal signal which is sent to the System
Interrupt Controller and is reflected via the
Interrupt Event (PHY_INT1)
PHYs, respectively. For more information on interrupts, refer to
page
PHY Power-Down Modes
There are two power-down modes for the PHY:
Note: For more information on the various power management features of the device, refer to
Note: The power-down modes of each PHY (Port 1 PHY and Port 2 PHY) are controlled
Note: The PHY power-down modes do not reload or reset the PHY registers.
Auto-Negotiation Complete
Parallel Detection Fault
INTERRUPT SOURCE
Remote Fault Detected
ENERGYON Activated
PHY General Power-Down
PHY Energy Detect Power-Down
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
55.
4.3, "Power Management," on page
independently.
Section 13.3.2, "Port 1 & 2 PHY Registers," on page 191
Table 7.3 PHY Interrupt Sources
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
and
enables or disables each PHY interrupt. The PHY Management Control
Port 2 PHY Interrupt Event (PHY_INT2)
DATASHEET
100
54.
Interrupt Status Register (INT_STS)
PHY_INTERRUPT_SOURCE_x REGISTER BIT #
2
C mode of operation) and allow access to all PHY
PHY_INTERRUPT_MASK_x &
Port x PHY Interrupt Mask Register
Chapter 5, "System Interrupts," on
7
6
5
4
3
2
1
for the Port 1 and Port 2
for a list of all supported
SMSC LAN9303/LAN9303i
shows the source of
Table
bits
7.3. Reading
Port 1 PHY
Datasheet
Section