LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 228

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
13.4.2.2
BITS
31:8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
Note:
RESERVED
Enable Receive Own Transmit
When set, the switch port will receive its own transmission if it is looped back
from the PHY. Normally, this function is only used in Half Duplex PHY
loopback.
RESERVED
Jumbo2K
When set, the maximum packet size accepted is 2048 bytes. Statistics
boundaries are also adjusted.
RESERVED
Reject MAC Types
When set, MAC control frames (packets with a type field of 8808h) are
filtered. When cleared, MAC Control frames, other than MAC Control Pause
frames, are sent to the forwarding process. MAC Control Pause frames are
always consumed by the switch.
RX Enable
When set, the receive port is enabled. When cleared, the receive port is
disabled.
Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
This read/write register configures the packet type passing parameters of the port.
This bit must always be written as 0.
Register #:
Port0: 0401h
Port1: 0801h
Port2: 0C01h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
228
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
SMSC LAN9303/LAN9303i
RO
RO
RO
RO
DEFAULT
Datasheet
0b
0b
0b
1b
1b
-
-
-
-