LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 212

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
13.4
REGISTER #
0006h-03FFh
0002h-0003h
0402h-040Fh
0000h
0001h
0004h
0005h
0400h
0401h
0410h
0412h
0413h
0411h
This section details the various switch control and status registers that reside within the Switch Fabric.
The switch control and status registers allow configuration of each individual switch port, the Switch
Engine, and Buffer Manager. Switch Fabric related interrupts and resets are also controlled and
monitored via the switch CSRs.
The switch CSRs are not memory mapped. All switch CSRs are accessed indirectly via the
Fabric CSR Interface Command Register
Register
(SWITCH_CSR_DIRECT_DATA)
the switch CSRs must be performed through these registers. Refer to
for additional information.
Note: The flow control settings of the switch ports are configured via the
Table 13.14
registers can be categorized into the following sub-sections:
Switch Fabric Control and Status Registers
Section 13.4.1, "General Switch CSRs," on page 223
Section 13.4.2, "Switch Port 0, Port 1, and Port 2 CSRs," on page 227
Section 13.4.3, "Switch Engine CSRs," on page 271
Section 13.4.4, "Buffer Manager CSRs," on page 317
MAC_RX_128_TO_255_CNT_0
MAC_RX_UNDSZE_CNT_0
Table 13.14 Indirectly Accessible Switch Control and Status Registers
MAC_RX_65_TO_127_CNT_0
1 Manual Flow Control Register
(MANUAL_FC_2), and
system CSR address space.
MAC_RX_64_CNT_0
(SWITCH_CSR_DATA), and
MAC_RX_CFG_0
MAC_VER_ID_0
lists the Switch CSRs and their corresponding addresses in order. The Switch Fabric
SW_DEV_ID
SW_RESET
RESERVED
RESERVED
RESERVED
SYMBOL
SW_IMR
SW_IPR
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Port 0 Manual Flow Control Register (MANUAL_FC_0)
General Switch CSRs
Switch Port 0 CSRs
in the system CSR memory mapped address space. All accesses to
DATASHEET
Switch Device ID Register,
Switch Reset Register,
Reserved for Future Use
Switch Global Interrupt Mask Register,
Switch Global Interrupt Pending Register,
Reserved for Future Use
Port 0 MAC Version ID Register,
Port 0 MAC Receive Configuration Register,
Reserved for Future Use
Port 0 MAC Receive Undersize Count Register,
Section 13.4.2.3
Port 0 MAC Receive 64 Byte Count Register,
Port 0 MAC Receive 65 to 127 Byte Count Register,
Section 13.4.2.5
Port 0 MAC Receive 128 to 255 Byte Count Register,
Section 13.4.2.6
212
(MANUAL_FC_1),
(SWITCH_CSR_CMD),
Switch Fabric CSR Interface Direct Data Registers
REGISTER NAME
Section 13.4.1.2
Port 2 Manual Flow Control Register
Section 13.4.1.1
Switch Fabric CSR Interface Data
Section 13.4.2.1
Section 13.2.4, "Switch Fabric"
Switch Fabric
Section 13.4.1.3
SMSC LAN9303/LAN9303i
Section 13.4.1.4
Section 13.4.2.2
Section 13.4.2.4
registers:
located in the
Datasheet
Switch
Port