LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 169

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.2.6
INDEX #
31
0
1
2
3
4
5
6
Virtual PHY
This section details the Virtual PHY System CSR’s. These registers provide status and control
information similar to that of a real PHY while maintaining IEEE 802.3 compatibility. The Virtual PHY
registers are addressable via the memory map, as described in
MII management protocol (IEEE 802.3 clause 22). When accessed serially, these registers are
accessed through the MII management pins (in PHY modes only) via the MII serial management
protocol specified in IEEE 802.3 clause 22. See
detailed description of the various device modes. When being accessed serially, the Virtual PHY will
respond when the PHY address equals the address assigned by the
strap, as defined in
indexes for serial access can be seen in
modes, refer to section
Section 7.3, "Virtual PHY," on page
Note: All Virtual PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management
Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII
VPHY_AN_LP_BASE_ABILITY
VPHY_BASIC_STATUS
VPHY_SPEC_CTRL_STATUS
register set. All functionality and bit definitions comply with these standards. The IEEE 802.3
specified register index (in decimal) is included under the memory mapped offset of each
Virtual PHY register as a reference. For additional information, refer to the IEEE 802.3
Specification.
management of PHY’s.
VPHY_BASIC_CTRL
VPHY_AN_ADV
VPHY_AN_EXP
VPHY_ID_MSB
Table 13.5 Virtual PHY MII Serially Adressable Register Index
VPHY_ID_LSB
SYMBOL
Section 7.1.1, "PHY Addressing," on page
Section
13.3. For Virtual PHY functionality and operation information, see
DATASHEET
102.
Virtual PHY Basic Control Register,
Virtual PHY Basic Status Register,
Virtual PHY Identification MSB Register,
Virtual PHY Identification LSB Register,
Virtual PHY Auto-Negotiation Advertisement Register,
Section 13.2.6.5
Virtual PHY Auto-Negotiation Link Partner Base Page Ability
Register,
Virtual PHY Auto-Negotiation Expansion Register,
Section 13.2.6.7
Virtual PHY Special Control/Status Register,
Table
169
Section 13.2.6.6
13.5. For more information on the Virtual PHY access
Section 2.3, "Modes of Operation," on page 19
REGISTER NAME
Table
88. A list of all Virtual PHY register
phy_addr_sel_strap
13.2, as well as serially via the
Section 13.2.6.2
Section 13.2.6.1
Section 13.2.6.4
Section 13.2.6.3
Revision 1.4 (07-07-10)
Section 13.2.6.8
configuration
for a