LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 317
LAN9303-ABZJ
Manufacturer Part Number
LAN9303-ABZJ
Description
IC ETHER SW 3PORT 16BIT 56QFN
Manufacturer
SMSC
Specifications of LAN9303-ABZJ
Controller Type
Ethernet Switch Controller
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
190mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Product
Ethernet Switches
Standard Supported
Yes
Data Rate
10 Mbps/100 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
0.19 A (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1095 - EVALUATION BOARD FOR LAN9303
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1082
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.4.4
13.4.4.1
BITS
31:7
4:2
6
5
1
0
RESERVED
BM Counter Test
When this bit is set, Buffer Manager (BM) counters that normally clear to 0
when read, will be set to 7FFF_FFFC when read.
Fixed Priority Queue Servicing
When set, output queues are serviced with a fixed priority ordering. When
cleared, output queues are serviced with a weighted round robin ordering.
Egress Rate Enable
When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch
ports 2,1,0 respectively.
Drop on Yellow
When this bit is set, packets that exceed the Ingress Committed Burst Size
(colored Yellow) are subjected to random discard.
Note:
Drop on Red
When this bit is set, packets that exceed the Ingress Excess Burst Size
(colored Red) are discarded.
Note:
Buffer Manager CSRs
This section details the Buffer Manager (BM) registers. These registers allow configuration and
monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their
corresponding register numbers is included in
Buffer Manager Configuration Register (BM_CFG)
This register enables egress rate pacing and ingress rate discarding.
See
Register (SWE_INGRSS_RATE_CMD)," on page 300
information on configuring the Ingress Committed Burst Size.
See
Register (SWE_INGRSS_RATE_CMD)," on page 300
information on configuring the Ingress Excess Burst Size.
Register #:
Section 13.4.3.26, "Switch Engine Ingress Rate Command
Section 13.4.3.26, "Switch Engine Ingress Rate Command
1C00h
DESCRIPTION
DATASHEET
317
Table
Size:
13.14.
for
for
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
RO
Revision 1.4 (07-07-10)
DEFAULT
0b
0b
0b
0b
0b
-
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