LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 271

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.4.3
13.4.3.1
BITS
31:3
2
1
0
RESERVED
Make Entry
When set, the contents of SWE_ALR_WR_DAT_0 and
SWE_ALR_WR_DAT_1 are written into the ALR table. The ALR logic
determines the location where the entry is written. This command can also
be used to change or delete a previously written or automatically learned
entry. This bit has no affect when written low. This bit must be cleared once
the ALR Make command is completed, which can be determined by the
Make Pending
(SWE_ALR_CMD_STS)
Get First Entry
When set, the ALR read pointer is reset to the beginning of the ALR table
and the ALR table is searched for the first valid entry, which is loaded into
the SWE_ALR_RD_DAT_0 and SWE_ALR_RD_DAT_1 registers. The bit
has no affect when written low. This bit must be cleared after it is set.
Get Next Entry
When set, the next valid entry in the ALR MAC address table is loaded into
the SWE_ALR_RD_DAT_0 and SWE_ALR_RD_DAT_1 registers. This bit
has no affect when written low. This bit must be cleared after it is set.
Switch Engine CSRs
This section details the Switch Engine related CSRs. These registers allow configuration and
monitoring of the various Switch Engine components including the ALR, VLAN, Port VID, and
DIFFSERV tables. A list of the general switch CSRs and their corresponding register numbers is
included in
Switch Engine ALR Command Register (SWE_ALR_CMD)
This register is used to manually read and write MAC addresses from/into the ALR table.
For a read access, the
Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)
Get First Entry
For write access, the
Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)
MAC address, followed by the setting of the
the
command is finished.
Refer to
Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)
Register #:
Chapter 6, "Switch Fabric," on page 59
Table
bit in the
bit or
13.14.
Get Next Entry
Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0)
Switch Engine ALR Command Status Register
register.
Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)
1800h
DESCRIPTION
DATASHEET
bit of this register.
271
Make Entry
Size:
for more information.
bit of this register. The
should be read following the setting of the
registers should first be written with the
32 bits
register indicates when the
TYPE
R/W
R/W
R/W
RO
Revision 1.4 (07-07-10)
Make Pending
DEFAULT
and
and
0b
0b
0b
-
Switch
Switch
bit in