LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 29

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
PINS
NUM
1
1
Port 0 Mode[0]
Output Data 0
Configuration
Output Data
Port 0 MII
Port 0 MII
NAME
Strap
Valid
P0_MODE0
P0_OUTDV
P0_OUTD0
SYMBOL
Table 3.4 Port 0 MII/RMII Pins (continued)
DATASHEET
BUFFER
Note 3.5
TYPE
(PU)
O8
O8
O8
O8
O8
O8
IS
29
MII MAC Mode: This pin is the transmit data 0 bit
from the switch to the external PHY.
MII PHY Mode: This pin is the receive data 0 bit
from the switch to the external MAC. The output
driver is disabled when the
is set in the
(VPHY_BASIC_CTRL).
RMII PHY Mode: This pin is the receive data 0 bit
from the switch to the external MAC. The output
driver is disabled when the
is set in the
(VPHY_BASIC_CTRL).
This strap configures the mode for Port 0. See
Note
The P0_MODE[2:0] configuration strap encoding is
as follows:
000 = MII MAC mode
001 = MII PHY mode
010 = MII PHY mode 200 Mbps 12 ma clock output
011 = MII PHY mode 200 Mbps 16 ma clock output
100 = RMII PHY mode clock is 12 ma output
101 = RMII PHY mode clock is 16 ma output
110 = RMII PHY mode clock is input
111 = RESERVED
MII MAC Mode: This pin is the TX_EN signal to the
external PHY and indicates valid data on
P0_OUTD[3:0].
MII PHY Mode: This pin is the RX_DV signal to the
external MAC. The output driver is disabled when
the
Basic Control Register
RMII PHY Mode: This pin is the CRS_DV signal to
the external MAC. The output driver is disabled
when the
Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
Isolate (VPHY_ISO)
3.4.
Isolate (VPHY_ISO)
Virtual PHY Basic Control Register
Virtual PHY Basic Control Register
DESCRIPTION
(VPHY_BASIC_CTRL).
bit is set in the
Isolate (VPHY_ISO)
Isolate (VPHY_ISO)
bit is set in the
Revision 1.4 (07-07-10)
Virtual PHY
bit
bit