LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 168

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
13.2.5.2
31:16
15:11
BITS
10:6
5:2
1
0
RESERVED
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to
"PHY Addressing," on page 88
assignments.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to
"Ethernet PHY Control and Status Registers," on page 191
descriptions on all PHY registers.
RESERVED
MII Write (MIIWnR)
Setting this bit informs the PHY that the access will be a write operation
using the
is cleared, the access will be a read operation, returning data into the
Management Interface Data Register
MII Busy (MIIBZY)
This bit must be read as 0 before writing to the
Data Register (PMI_DATA)
(PMI_ACCESS)
written. During a PHY register access, this bit will be set, signifying a read
or write access is in progress. This is a self-clearing (SC) bit that will return
to 0 when the PHY register access has completed.
During a PHY register write, the
(PMI_DATA)
During a PHY register read, the
(PMI_DATA)
PHY Management Interface Access Register (PMI_ACCESS)
This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the
Register (PMI_DATA)
Note: The Virtual PHY registers are NOT accessible via these registers.
PHY Management Interface Data Register
Offset:
must be kept valid until this bit is cleared.
register is invalid until the MAC has cleared this bit.
registers. This bit is automatically set when this register is
to perform read and write operations to the PHYs.
or
0A8h
DESCRIPTION
PHY Management Interface Access Register
for information on PHY address
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
PHY Management Interface Data Register
PHY Management Interface Data Register
DATASHEET
(PMI_DATA).
168
PHY Management Interface
Size:
(PMI_DATA). If this bit
for detailed
Section 7.1.1,
Section 13.3,
32 bits
PHY
PHY Management Interface Data
TYPE
R/W
R/W
R/W
SMSC LAN9303/LAN9303i
RO
RO
RO
SC
DEFAULT
00000b
00000b
Datasheet
0b
0b
-
-