LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 276

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
13.4.3.5
31:27
21:19
BITS
26
25
24
23
22
RESERVED
Valid
This bit is cleared when the
Switch Engine ALR Command Register (SWE_ALR_CMD)
bit is set when a valid entry is found in the ALR table. This bit stays cleared
when the top of the ALR table is reached without finding an entry.
End of Table
This bit indicates that the end of the ALR table has been reached and further
Get Next Entry commands are not required.
Note:
Static
Indicates that this entry will not be removed by the aging process. When this
bit is cleared, this entry will be automatically removed after 5 to 10 minutes
of inactivity. Inactivity is defined as no packets being received with a source
address that matches this MAC address.
Filter
When set, indicates that packets with a destination address that matches
this MAC address will be filtered.
Priority Enable
Indicates whether or not the usage of the
MAC address entry.
Priority
These bits specify the priority that is used for packets with a destination
address that matches this MAC address. This priority is only used if both the
Priority Enable
Switch Engine Global Ingress Configuration Register
(SWE_GLOBAL_INGRSS_CFG)
Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)
This register is used in conjunction with the
(SWE_ALR_RD_DAT_0)
loaded via the Get First Entry or Get Next Entry commands in the
Register
set.
The Valid bit may or may not be set when the end of the table is
reached.
Register #:
(SWE_ALR_CMD). This register is only valid when either of the Valid or End of Table bits are
bit of this register and the
to read the ALR table. It contains the last 32 bits of the ALR entry and is
Get First Entry
1806h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
are set.
DATASHEET
DA Highest Priority
Priority
or
276
Get Next Entry
Size:
field is enabled for this
Switch Engine ALR Read Data 0 Register
are written. This
bit in the
bits of the
32 bits
Switch Engine ALR Command
TYPE
SMSC LAN9303/LAN9303i
RO
RO
RO
RO
RO
RO
RO
DEFAULT
000b
Datasheet
0b
0b
0b
0b
0b
-