LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 89

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
7.2
To MII Mux
To Port x
Switch Fabric MAC
The Port 1 and Port 2 PHYs are functionally identical and can be divided into the following functional
sections:
Note 7.1
A block diagram of the Port x PHYs main components can be seen in
Port 1 & 2 PHYs
MDIO
MII
100BASE-TX Transmit
10BASE-T Transmit
PHY Auto-negotiation
HP Auto-MDIX
MII MAC Interface
PHY Management Control
Registers
Interface
PHY Management
Negotiation
Because the Port 1 PHY and Port 2 PHY are functionally identical, this section will describe
them as the “Port x PHY”, or simply “PHY”. Wherever a lowercase “x” has been appended
to a port or signal name, it can be replaced with “1” or “2” to indicate the Port 1 or Port 2
PHY respectively. All references to “PHY” in this section can be used interchangeably for
both the Port 1 & 2 PHYs. This nomenclature excludes the Virtual PHY.
MAC
MII
Auto-
Control
Interrupt Controller
To System
Interrupts
Figure 7.1 Port x PHY Block Diagram
and
and
10BASE-T Receive
100BASE-TX Receive
Transmitter
Reciever
10/100
10/100
DATASHEET
To GPIO/LED
89
Controller
LEDs
HP Auto-MDIX
From
System Clocks Controller
PLL
Figure
TXPx/TXNx
RXPx/RXNx
7.1.
Revision 1.4 (07-07-10)
To External
Port x Ethernet Pins