LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 190

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
13.2.7.7
BITS
31:4
3
2
1
0
RESERVED
Virtual PHY Reset (VPHY_RST)
Setting this bit resets the Virtual PHY. When the Virtual PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is set.
Note:
Port 2 PHY Reset (PHY2_RST)
Setting this bit resets the Port 2 PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port 2 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note:
Port 1 PHY Reset (PHY1_RST)
Setting this bit resets the Port 1 PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port 1 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note:
Digital Reset (DIGITAL_RST)
Setting this bit resets the complete chip except the PLL, Virtual PHY, Port 1
PHY, and Port 2 PHY. The EEPROM Loader will automatically reload the
configuration following this reset, but will not reset the Virtual PHY, Port 1
PHY, or Port 2 PHY. If desired, the above PHY resets can be issued once
the device is configured. All system CSRs are reset except for any NASR
type bits. Any in progress EEPROM commands (including RELOAD) are
terminated.
When the chip is released from reset, this bit is automatically cleared. The
Byte Order Test Register (BYTE_TEST)
the reset is complete. All writes to this bit are ignored while this bit is set.
Note:
Reset Control Register (RESET_CTL)
This register contains software controlled resets.
Note: This register can be read while the device is in the not ready state. This register can also be
Note: In SMI mode, either half of this register can be read without the need to read the other half.
This bit is not accessible via the EEPROM Loader.
This bit is not accessible via the EEPROM Loader.
This bit is not accessible via the EEPROM Loader.
This bit is not accessible via the EEPROM Loader.
polled while the device is in the reset state without causing any damaging effects. However,
the returned data will be invalid since the serial interfaces are also in the reset state at this
time.
Offset:
1F8h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
should be polled to determine when
190
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
SMSC LAN9303/LAN9303i
RO
SC
SC
SC
SC
DEFAULT
Datasheet
0b
0b
0b
0b
-