LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 65

IC ETHER SW 3PORT 16BIT 56QFN

LAN9303-ABZJ

Manufacturer Part Number
LAN9303-ABZJ
Description
IC ETHER SW 3PORT 16BIT 56QFN
Manufacturer
SMSC
Datasheets

Specifications of LAN9303-ABZJ

Controller Type
Ethernet Switch Controller
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
190mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Product
Ethernet Switches
Standard Supported
Yes
Data Rate
10 Mbps/100 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
0.19 A (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1095 - EVALUATION BOARD FOR LAN9303
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1082

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
6.3.1.1
"Flow Control Enable Logic," on page
to the Switch Engine. Non-pause control frames are optionally filtered or forwarded.
When the receive FIFO is full and additional data continues to be received, an overrun condition occurs
and the frame is discarded (FIFO space recovered) or marked as a bad frame.
The receive MAC can be disabled from receiving all frames by clearing the
x MAC Receive Configuration Register
The size of the RX FIFO is 256 bytes. If a bad packet with less than 64 bytes is received, it will be
flushed from the FIFO automatically and the FIFO space recovered. Packets equal to or larger than
64 bytes with an error will be marked and reported to the Switch Engine. The Switch Engine will
subsequently drop the packet.
Receive Counters
The receive MAC gathers statistics on each packet and increments the related counter registers. The
following receive counters are supported for each Switch Fabric port. Refer to
Accessible Switch Control and Status Registers,” on page 212
Section 13.4.2.22
Total undersized packets
Total packets 64 bytes in size
Total packets 65 through 127 bytes in size
Total packets 128 through 255 bytes in size
Total packets 256 through 511 bytes in size
Total packets 512 through 1023 bytes in size
Total packets 1024 through maximum bytes in size
Total oversized packets
Total OK packets
Total packets with CRC errors
Total multicast packets
Total broadcast packets
Total MAC Pause packets
Total fragment packets
Total jabber packets
Total alignment errors
Total bytes received from all packets
Total bytes received from good packets
Total packets with a symbol error
Total MAC control packets
for detailed descriptions of these counters.
(Section 13.4.2.11, on page
(Section 13.4.2.17, on page
(Section 13.4.2.18, on page
(Section 13.4.2.13, on page
(Section 13.4.2.16, on page
(Section 13.4.2.10, on page
(Section 13.4.2.14, on page
(Section 13.4.2.3, on page
(Section 13.4.2.15, on page
(Section 13.4.2.22, on page
(Section 13.4.2.4, on page
(Section 13.4.2.12, on page
DATASHEET
(Section 13.4.2.21, on page
62. Pause frames are consumed by the MAC and are not sent
(MAC_RX_CFG_x).
(Section 13.4.2.19, on page
65
(Section 13.4.2.20, on page
(Section 13.4.2.5, on page
(Section 13.4.2.7, on page
(Section 13.4.2.6, on page
(Section 13.4.2.8, on page
237)
243)
244)
(Section 13.4.2.9, on page
239)
242)
236)
229)
240)
241)
248)
230)
238)
247)
245)
and
246)
231)
Section 13.4.2.3
233)
232)
RX Enable
234)
Table 13.14, “Indirectly
Revision 1.4 (07-07-10)
235)
bit of the
through
Port

Related parts for LAN9303-ABZJ