LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 31

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
PINS
NUM
1
1
1
1
Carrier Sense
Management
Management
Input/Output
Port 0 MII
Port 0 MII
Note 3.4
Note 3.5
Duplex
NAME
Clock
Data
MII
Configuration strap pins are identified by an underlined symbol name. Configuration strap
values are latched on power-on reset or nRST de-assertion. Additional strap pins, which
share functionality with the GPIO/LED pins, are described in
straps can be overridden by values from the EEPROM Loader. Please refer to
4.2.4, "Configuration Straps," on page 45
An external supplemental pull-up may be needed, depending upon the input current
loading of the external MAC/PHY device.
P0_DUPLEX
SYMBOL
P0_CRS
MDIO
Table 3.4 Port 0 MII/RMII Pins (continued)
MDC
DATASHEET
BUFFER
TYPE
IS/O8
(PD)
(PU)
(PU)
O8
O8
IS
IS
IS
IS
-
31
MII MAC Mode: This pin is an input from the
external PHY indicating a network carrier.
MII PHY Mode: This pin is an output to the external
MAC indicating a network carrier. The output driver
is disabled when the
in the
(VPHY_BASIC_CTRL).
RMII PHY Mode: This pin is not used.
MII MAC Mode: This pin can be changed at any
time (live value) and can be overridden by enabling
the
PHY Basic Control Register
(VPHY_BASIC_CTRL). It is typically tied to the
duplex indication from the external PHY. Please
refer to the definition of the
for further details.
MII PHY and RMII PHY Modes: This pin is used
to determine the virtual link partner’s ability bits and
is typically tied high or low, as needed. Please refer
to the definition of the
further details.
SMI/MII Slave Management Modes: This is the
data to/from an external master
MII Master Management Modes: This is the data
to/from an external PHY.
Note:
Note:
SMI/MII Slave Management Modes: This is the
clock input from an external master.
Note:
MII Master Management Modes: This is the clock
output to an external PHY.
Auto-Negotiation (VPHY_AN)
for further information.
Virtual PHY Basic Control Register
An external pull-up is required when the
SMI or MII management interface is used,
to ensure that the IDLE state of the MDIO
signal is a logic one.
An external pull-up is recommended when
the SMI or MII management interface is
not used, to avoid a floating signal.
When SMI or MII is not used, an external
pull-down is recommended to avoid a
floating signal.
DESCRIPTION
Isolate (VPHY_ISO)
DUPLEX_POL_0
Table
DUPLEX_POL_0
3.5. Some configuration
Revision 1.4 (07-07-10)
bit in the
strap for
bit is set
Virtual
Section
strap