LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 200

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
autoneg_strap_x
BITS
4:0
0
0
0
0
1
1
1
1
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13.59 The Asymmetric Pause and Symmetric Pause bits are loaded into the PHY registers by
Note 13.60 The default value of this bit is determined by the logical OR of the Auto-Negotiation Enable
Note 13.61 The default value of this bit is determined by the logical OR of the Auto-Negotiation Enable
Table 13.9 10BASE-T Full Duplex Advertisement Default Value
speed_strap_x
the EEPROM Loader. The default values of the Asymmetric Pause and Symmetric Pause
bits are determined by the Manual Flow Control Enable Strap
1 PHY,
is 0, the Symmetric Pause bit defaults to 1 and the Asymmetric Pause bit defaults to the
setting of the Full Duplex Flow Control Enable Strap
FD_FC_strap_2
bits default to 0. Configuration strap values are latched upon the de-assertion of a chip-
level reset as described in
Section 4.2.4, "Configuration Straps," on page 45
strap
AND of the negated Speed Select strap
Port 2 PHY) and the Duplex Select Strap
for Port 2 PHY).
values are latched upon the de-assertion of a chip-level reset as described in
4.2.4, "Configuration Straps," on page
on page 45
strap
Speed Select strap
Table 13.10
upon the de-assertion of a chip-level reset as described in
Straps," on page
configuration strap definitions.
(autoneg_strap_1
(autoneg_strap_1
0
0
1
1
0
0
1
1
manual_FC_strap_2
for configuration strap definitions.
defines the default behavior of this bit. Configuration strap values are latched
DESCRIPTION
for Port 2 PHY). When the Manual Flow Control Enable Strap is 1, both
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Table 13.9
45. Refer to
duplex_strap_x
(speed_strap_1
DATASHEET
for Port 1 PHY,
for Port 1 PHY,
0
1
0
1
0
1
0
1
for Port 2 PHY). When the Manual Flow Control Enable Strap
Section 4.2.4, "Configuration Straps," on page
defines the default behavior of this bit. Configuration strap
200
Section 4.2.4, "Configuration Straps," on page 45
for Port 1 PHY,
45. Refer to
autoneg_strap_2
(speed_strap_1
autoneg_strap_2
(duplex_strap_1
Default 10BASE-T Full Duplex Value
for configuration strap definitions.
Section 4.2.4, "Configuration Straps,"
(FD_FC_strap_1
speed_strap_2
for Port 1 PHY,
for Port 2 PHY) and the negated
for Port 2 PHY) with the logical
for Port 1 PHY,
(manual_FC_strap_1
Section 4.2.4, "Configuration
0
1
0
0
1
1
1
1
TYPE
R/W
SMSC LAN9303/LAN9303i
speed_strap_2
for Port 2 PHY).
for Port 1 PHY,
duplex_strap_2
DEFAULT
45. Refer to
00001b
Datasheet
Section
for Port
for
for