LSISASX12 LSI, LSISASX12 Datasheet - Page 101

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4040
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DS
This register allows the host to manually read and control the SCL and
SDA API2C interface signals.
R
SDAE
SCLE
SDAC
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Divider Select
This field selects the bit position from a 16-bit counter to
use as an enable for the timers. Bit 3 is the most signifi-
cant bit (MSB).
Reserved
These bits are reserved.
SDA Falling Edge Detect
A 1 in this bit indicates that at least one HIGH-to-LOW
transition has occurred on the SDA status line. Writing a
1 to this bit clears it.
SCL Falling Edge Detect
A 1 in this bit indicates that at least one HIGH-to-LOW
transition has occurred on the SCL status line. Writing a
1 to this bit clears it.
SDA Control
This bit controls the SDA signal.
SDAC
0
1
API2C Monitor
Function
SDA is not forced LOW.
SDA is forced LOW on the API2C
interface.
16 15
8 7
0
0 0 0 0
[31:6]
0
[3:0]
4-23
0
0
5
4
3