LSISASX12 LSI, LSISASX12 Datasheet - Page 40

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

2-18
The API2C interface operates as a master only with 100 kHz or 400 kHz
memories that support 16-bit addressing. The base vector is always read
at a 100 kHz rate. If the most significant bit is set, the remaining data is
read at 400 kHz. If a failure occurs, the configuration manager retries the
read. After three retries, all subsequent read attempts are at 100 kHz.
Figure 2.3
boot record are 8 bits wide.
Figure 2.3
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
lSTWI Address 0 Base Vector
lSTWI Address 1 Base Vector
lSTWI Address 2 Base Vector
lSTWI Address 3Base Vector
null ptr (0b00000000)
Optional Data Field
Fixed Data Field
shows the format of the boot record. The data fields in the
Structure N
Checksum
Checksum
Boot Record Format
0x00
0x01
0x02
0x03
Base + 0x00
Base + 0xN1
Base + 0xN2
Base + 0xN2+optlen
Base + 0xN2+optlen+0x01
The null pointer and second checksum is required
Speed
CMD: Write DWORD
CMD: Write Block
CMD: Set Base Address
BlockBase (Addr/64)
seq
seq
seq
Addr[7:2]
Addr[7:2]
WORD 0 [31:24]
WORD 0 [31:24]
0
1
1
DWORD n [7:0]
Length (DWORDs)
Data[31:24]
Data[23:16]
reserved
Addr[18:12]
Data[15:8]
Data[7:0]
1
0
1
Addr[11:8]
Addr[11:8]
reserved