LSISASX12 LSI, LSISASX12 Datasheet - Page 242

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

A-2
Table A.1
Register Summary
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Register Name
Phy Transmit Polarity
Phy Receiver Polarity
Boot Control and Status
Reserved
API2C Global Control
API2C Interrupt Status
API2C Interrupt Enable
API2C Wait Timer Control
API2C t
API2C t
API2C Timer Clock Divider Control
API2C Monitor
API2C Soft Reset
API2C Master Command
API2C Receive Transfer Length
API2C Transmit Transfer Length
API2C Address Register 1
API2C Address Register 2
API2C Data
API2C Transmit FIFO Status
API2C Receive FIFO Status
API2C Master Interrupt Enable
API2C Master Interrupt Status
API2C Transmit Bytes Transferred
API2C Receive Bytes Transferred
TIMEOUT
LOW
Control
Configuration Manager Config Register Map (Cont.)
Control
Offset
0x004C
0x0050
0x0090
–
0x4000
0x4008
0x4010
0x4018
0x4020
0x4028
0x4038
0x4040
0x4048
0x4050
0x4058
0x4060
0x4068
0x4070
0x4078
0x4080
0x4088
0x4090
0x4098
0x40A0
0x40A8
Page
4-15
4-16
4-16
–
4-17
4-18
4-19
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-29
4-30
4-30
4-31
4-32
4-35
4-36