LSISASX12 LSI, LSISASX12 Datasheet - Page 112

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

4-34
AL
ND
NA
TS
STP
TTP
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Note:
After an API2C timer time-out during a master read
operation, this bit sets when the Stop condition appears on
the interface.
This bit clears when it is read or when a new command
is issued.
Arbitration Lost
This bit sets to 1 if any data transfer command loses
API2C interface arbitration. This bit clears to 0 when it is
read or when a new command is issued.
NAK Received During Transmit Data Phase
This bit sets to 1 if any data transfer command receives
a NAK during the transmit data phase of an API2C inter-
face transaction. This bit clears to 0 when it is read or
when a new command is issued.
NAK Received During Address Phase
This bit sets to 1 if any data transfer command receives
a NAK during the address phase of an API2C interface
transaction. This bit clears to 0 when it is read or when a
new command is issued.
Transfer Stopped
This bit indicates that a Stop command terminated the
transfer. This bit is the logical OR of bits 15, 14, and
[10:4] of this register and is read only.
Sequence Transfer in Process
This bit indicates that a Sequence Transfer command
data sequence (Write/Read) is in process.
This bit sets to 1 at the start of the transmit portion of a
sequence command. This bit clears to 0 when the receive
portion of a sequence command completes and this reg-
ister is read.
Transmit Transfer in Process
This bit indicates that the master state machine is pro-
cessing the transmit (write) part of a data transfer.
This bit sets to 1 at the start of the transmit transfer. The
bit clears to 0 when either the transmit transfer completes
and this register is read, or when a Sequence Transfer
command switches to the receive part of the transfer.
6
5
4
3
2
1