LSISASX12 LSI, LSISASX12 Datasheet - Page 232

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Table 5.21
Signal
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
1. NC pins are not connected inside of the package.
2. Boot load options configure the polarity of the RX+/RX signals and TX+/TX signals for each phy
5-10
through the
CBL_DET[11]/
CBL_DET[10]/
CBL_DET[9]/
CBL_DET[8]/
CBL_DET[5]/
CBL_DET[6]/
CBL_DET[3]/
CBL_DET[7]/
SCANCLK3
VDDIO33
VDDIO33
VDDIO33
MODE[1]
MODE[0]
MODE[3]
MODE[2]
PLLVDD
PLLVSS
Listing by Pin Number
RX[6]+
RX[6]
TX[5]+
TX[6]+
Phy Transmit Polarity
IDDT
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Specifications
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Signal
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
SCAN_ENABLE
CBL_DET[2]/
CBL_DET[4]/
CBL_DET[1]/
CBL_DET[0]/
and
SCANCLK1
PROCMON
RXVDD[6]
RXVDD[5]
RXVDD[7]
UART_RX
TXVDD[5]
TXVDD[6]
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
1, 2
RX[5]+
RX[5]
TX[5]
TX[6]
TRST/
Phy Receiver Polarity
TDO
TMS
Pin
VSS
VSS
VSS
TCK
TDI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TN
Signal
E21
E22
E23
E24
E25
E26
F1
F2
F3
F4
F5
F6
F7
F8
F9
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
G2
G3
G4
G5
G6
G7
G8
G19
G20
G21
G22
G23
G24
G25
G26
H1
H2
H3
H4
H5
H6
H7
H20
H21
H22
H23
H24
H25
H26
J1
J2
J3
J4
J5
J6
J21
SCAN_MODE
SCANCLK2
RXBVDD[5]
RXBVDD[7]
RXBVDD[6]
RXBVSS[7]
RXBVSS[6]
RXBVSS[5]
TXBVDD[5]
TXBVDD[6]
TXBVDD[8]
RXBVSS[8]
TXBVDD[7]
RXBVSS[4]
registers.
TXBVSS[6]
TXBVSS[7]
TXBVSS[5]
RXVDD[4]
RXVSS[5]
RXVSS[6]
RXVSS[4]
TXVDD[4]
TXVDD[7]
RXVSS[7]
UART_TX
TXVSS[6]
TXVSS[5]
TXVSS[7]
RX[4]
RX[4]+
RX[7]+
RX[7]
TX[7]+
TX[4]+
TX[7]
TX[4]
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Signal
J22
J23
J24
J25
J26
K1
K2
K3
K4
K5
K22
K23
K24
K25
K26
L1
L2
L3
L4
L5
L22
L23
L24
L25
L26
M1
M2
M3
M4
M5
M12
M13
M14
M15
M22
M23
M24
M25
M26
N1
N2
N3
N4
N5
N12
N13
N14
N15
N22
N23
N24
N25
N26
P1
P2
P3
P4
P5
P12
P13
P14
RXBVDD[4]
RXBVDD[8]
RXBVDD[3]
TXBVDD[4]
RXBVSS[3]
TXBVDD[3]
RXBVSS[9]
TXBVSS[8]
TXBVSS[4]
TXBVSS[3]
RXVDD[3]
RXVDD[8]
RXVSS[8]
RXVSS[3]
TXVDD[8]
TXVSS[4]
TXVSS[8]
TXVSS[3]
RX[3]
RX[3]+
RX[8]+
RX[8]
RX[9]
RX[2]
RX[2]+
RX[9]+
TX[3]+
TX[3]
TX[8]
TX[8]
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC