LSISASX12 LSI, LSISASX12 Datasheet - Page 54

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

2.7.4
Figure 2.7
2-32
S
S
A
Master to Slave
Slave to Master
Control
Control
Byte
Byte
Data_0
I
2
C Slave Write Operations
Slave Write Operation
W
W
A
A
A
enabled and the LSISASx12 detects a bad CRC value, the LSISASx12
asserts the EMB_CRC_INT signal to notify the SEP of the error.
Figure 2.7
transfers, the fourth data byte of the transfer contains the CRC. The CRC
is calculated using the control byte (0b1010_0A
byte, Address_Lo byte, and the data byte. The LSISASx12 does not
commit the data until it validates the payload CRC.
Block transfers use two CRC bytes: the header CRC and the payload
CRC. The header CRC covers the address and the byte count; the
payload CRC covers the data. The fourth byte of the transfer contains
the header CRC. If the LSISASx12 detects an error in the address or
byte count, it asserts the EMB_CRC_INT signal. The data transfer can
continue, but the LSISASx12 discards the data. The LSISASx12 resets
the CRC calculation for the data transfer portion of the block write
operation. The payload CRC byte is the last data byte before the I
master signals a stop condition.
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
BLK=0 Addr_Hi
BLK=1 Addr_Hi
S = Start Condition
P = Stop Condition
A = Acknowledge
R = Read
W = Write
illustrates an I
A
A
A
Addr_Lo
Addr_Lo
Block Write
Data_n
Byte Write
2
C slave write operation. For byte write
A
A
A
Byte Count = n
Payload CRC
Data_0
1
A
A
A
A
0
0), the Address_Hi
P
Payload CRC
Header CRC
A
2
C
P