LSISASX12 LSI, LSISASX12 Datasheet - Page 135

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0xC004
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
SIO Enable
Setting this bit selects SIO functionality for the SIO pins.
SIO Mode
This bit indicates the SIO mode. Clearing this bit config-
ures the SIO for a single participant. Setting this bit con-
figures the SIO for multiple participants.
First SIO Device
This bit is set to indicate that the device is the first SIO
data transmitter (First Originator), and can append mux
control codes to the SioEnd signal. When this bit is
cleared, the device can not append mux control codes to
the SioEnd signal, but must pass on any codes it
receives.
SIO Receive 0
The SIO receive registers (SIO_RCV0 and SIO_RCV1)
receive data directly from the serial SIO at the end of
each normal serial input/output cycle. The number of bits
shifted in (and therefore the number of valid inputs bits)
is 3 times the SIO Device Count. The SIO Device Count
is located in the
Bits [(((SioDeviceCnt) * 3) – 1):0] of this register contain
the data shifted in during the most recent serial input/out-
put cycle. When the SIO Device Count is set to 10 or 11,
bits [31:0] of this register contain the data from bits [31:0]
of the input shift register, and the rest of the bits are avail-
able in the
SIO Receive 0
16 15
SIO Receive 1
SIO Configuration
register.
8 7
register.
0
0 0 0 0
[31:0]
0
4-57
0
0
2
1
0